Memory subsystem performance is an important factor in the overall performance of computer systems. This may be particularly true in computer systems that integrate a graphics controller in a component along with a memory controller. The graphics device accesses graphics memory located within system memory through the memory controller.
The graphics controller may issue 32 Byte “stride cycles” to the memory controller. This type of cycle may be defined as 32 Byte read requests whose two 16 Byte addresses are offset by plus or minus 128 Bytes (or 256 Bytes) instead of a usual offset of 16 Bytes. Also, these stride cycles are typically sequenced with another stride cycle which is either 16 Bytes of 32 Bytes apart from the previous cycle. In prior computer systems using double data rate (DDR) memory, the two stride cycles are separated by a wait state of one clock period.